Re: gcc -MM and Makefiles

From: Daniel A. Koepke (dkoepke@california.com)
Date: 09/20/99


On Sep 18, Vrallis spake to the list:

> [snip]

Well, as long as you're using GNU stuff for everything, you may as well
take advantage of some of the benefits GNU Make gives you!

> OBJFILES = \
>         act.comm.o \
>         act.informative.o \
>         act.item.o \
> ............
>         zedit.o
>
> C_FILES = \
>         act.comm.c \
>         act.informative.c \
>         act.item.c \
> ............
>         zedit.c

Ick, why duplicate this crap?

    OBJFILES := act.comm.o ...
    C_CFILES := $(patsubst %.o,%.c,$(OBJFILES))

Or, if you're like me:

    OBJDIR := objs
    CFILES := act.comm.c ...
    OBJS := $(foreach obj,$(patsubst %.c,%.o,$(CFILES)),$(OBJDIR)/$(obj))

and then the generic rule:

    $(OBJDIR)/%.o: %.c conf.h sysdep.h
    <tab>$(CC) -c $(CFLAGS) $< -o $@

Where the variable $(OBJS) replaces every instance of $(OBJFILES).  I
only changed it so the "OBJS := ..." line didn't wrap.  This created the
.o files in the $(OBJDIR) directory, which is useful to keep your src/
directory uncluttered.  By using the GNU Make functions (foreach,
patsubst, etc.) it's compact and fairly automatic.  I wrote the
dependencies with:

    echo -n "\$$(OBJDIR)/" >> Depend.mak
    $(CC) -MM $< >> Depend.mak

Where $< is the C file.

-dak


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